1. Field of the Invention
The present invention pertains to wafer polishing, and especially to the planarization of semiconductor wafers and the like thin, flat workpieces.
2. Description of the Related Art
As is known in the art, many types of semiconductor devices are made by stacking multiple thin layers one on top of the other using metalization, sputtering, ion implantation and other techniques. The thicknesses of such layers are very small, typically on the order of several molecular dimensions. These techniques allow integrated circuits to be made up of multiple millions of circuit devices which are typically formed in a semiconductor substrate which is relatively thin and therefore fragile. For example, commercial semiconductor wafers may have a diameter of six or eight inches, having a thickness on the order of several thousandths of an inch or less. In practical production, the flatness of such wafers is typically held to 120 micro inches or less. As is known in the art, flatness or global planarity is achieved by abrading the wafer surface so as to remove high spots. However, it must be borne in mind that the coatings applied to the wafer may be as thin as 30 micro inches, held to an accuracy (or variation in thickness) of roughly 1/100 of the thickness of the coating. As is apparent from the above considerations, great care must be taken in polishing a semiconductor wafer.
The SpeedFam Corporation of Chandler, Ariz., assignee of the present invention, is a manufacturer of equipment for planarizing wafers using chemical/mechanical polishing (CMP) and other techniques. In polishing wafers, typically of semiconductor material such as silicon, the wafer is placed face down on a polish pad carried on a rotating, driven table. A chemically active media, frequently referred to as a "slurry" and oftentimes containing abrasive particles, is introduced between the wafer and the polishing pad. A polishing force is applied to the back side of the wafer, pressing the wafer against the polish pad. Polishing force is typically applied by a relatively massive polish head, with a backing pad interposed between the polish head and the back side of the wafer.
During the polishing process, portions of the wafer surface protruding from a theoretical truly flat plane are removed, with resulting wafer particles being suspended in the slurry. The material removal rate during polishing depends on a number of factors, the primary factor being the down force applied to the wafer, pressing the wafer against the polish pad. As has been observed over the years, careful controlling of the down force over the entire surface of the wafer is important if global planarity is to be achieved with an acceptable amount of material removal.
As mentioned, the wafers being polished are relatively thin and, depending upon their physical composition and the composition and proportion of layers deposited therein, have varying degrees of stiffness. Even with the stiffer wafer compositions, it is oftentimes possible with close scrutiny to observe variations in the backing pad or pressure head to "print through" or otherwise be reflected in the surface of the wafer being polished. While articulated backing arrangements such as those described in U.S. Pat. Nos. 5,441,444, 5,584,746 and 5,651,724 provide advances in providing enhanced control of down forces throughout the entire wafer surface, the risk of print-through is substantially increased.
The assignee of the present invention has provided significant advances in improving backing pad flatness, using a number of pre-operational techniques to "dress" the active backing pad surface. Cost control measures are being applied throughout the entire semiconductor device production, and backing pads are being scrutinized on a cost basis as consumable goods requiring substantial cost outlays in material and labor. As mentioned above, particles removed from a semiconductor surface are suspended in the slurry surrounding the wafer being polished. Such particles inevitably migrate between the back side of the wafer and the backing pad, becoming embedded in the backing pad surface. To a certain extent, backing pads exhibit a limited resilience which is altered in a non-controlled, non-uniform manner throughout the life of the backing pad. Particle embedding and other forces operate to create localized "hard spots" in the surface of the backing pad and over repeated polishing operations, deterioration of the backing pad becomes increasingly aggravated, eventually requiring replacement of the backing pad.
Typically, backing pads are secured to the pressure plate with a pressure sensitive adhesive. Removal of a used backing pad, therefore, requires removal of its associated sealing layer from the surface of the pressure plate so that the highly controlled flatness of the pressure plate surface can be fully restored in preparation for the installation of a new backing pad. A new sealing layer must thereafter be applied to the pressure plate surface with sufficient exactness so as to avoid destroying the carefully controlled flatness or "global planarity" of the pressure plate and working surface of the new backing pad. While various techniques are available to "dress" the backing pad surface after its installation so as to account for irregularities in adhesive thickness, the ability to correct such flatness excursions is limited.
Accordingly, attention has been directed to the possibility of replacing backing pad systems with an alternative system offering cost advantages. Several of the patents referred to above attempt to replace conventional backing pads with a flexible sheet or other bladder construction pressurized by a fluid, such as water, or gas, such as air. Various arrangements have been proposed for use in wafer planarization in which a single bladder is made to cover substantially the entire wafer back surface. Examples of such arrangements are found in U.S. Pat. Nos. 5,449,316 and 5,635,083. Despite such efforts, backing pad assemblies continue to dominate the semiconductor wafer polishing industry as the preferred mode for supporting the wafer during chemical/mechanical polishing. Other arrangements in which the flexible membrane or bladder is provided with non-uniform resilient characteristics such as proposed in U.S. Pat. No. 5,624,299 have been considered in an attempt to improve the performance of the overall system.
Typically, semiconductor wafers are polished many times during the course of semiconductor device fabrication. As multiple layers of conductors and dielectrics are built up on the surface of a wafer, polishing is usually required after the deposition of each layer to restore any deviation from highly demanding local and global flatness tolerances. Because so-called "out-of-flatness" tolerances must be related to the total, finished construction, it is critical that the polishing process be held to extremely close tolerances such that finished densely packed structures do not interfere with one another.
It is important, during the course of preparing the semiconductor surface, that proper amounts of polishing are applied to assure that the desired degree of flatness is attained without undesirable intrusion into the deposited layers, which might compromise their intended electronic operation. While it is possible to periodically remove the wafer being processed from the polishing apparatus in order to inspect the wafer surface, such practices are undesirable in that they subject the wafer to additional handling with an attendant risk of injury. Further, the environmental condition of the wafer must be taken into account. For example, wafers being processed are oftentimes maintained immersed in an aqueous environment. In order to facilitate remote inspection of the wafer, the wafer would have to be removed from the aqueous environment, cleaned, and dried to facilitate inspection. Care must be taken to guard against distortion of the wafer, and the introduction of wet/dry cycles may give rise to unwanted distortion and may introduce harmful contamination.
In order to overcome these drawbacks, attention has been directed to so-called in-situ end point detection. A variety of techniques have been developed over the years. For example, various electrical signals have been passed through the wafer and the area of polishing activity, with the electrical signal thereby being modified in a certain manner, dependent upon the amount of polishing of the wafer surface. In general, such techniques rely upon an indirect detection of the wafer surface characteristics. Correlation of various modifications of the electrical signal to the wafer surface characteristics typically requires considerable experience and intense research for each particular process being carried out. Changes in polishing conditions (for example changes in slurry composition, abrasive structures, polish wheel compositions and the like) oftentimes require additional study with new correlation techniques being developed in order to indirectly indicate the surface condition of the wafer being processed in an accurate manner.
The outer edges of semiconductor wafers have been monitored on a real-time basis. Wafers mounted on reciprocating arms are carried to the edge of a polishing table, and slightly beyond by the reciprocating action. Thus, for a brief instant with each cycle of reciprocation, the bottom surface of the wafer is exposed to a monitoring probe located immediately adjacent the edge of the polishing wheel. However, only a relatively minor outer portion of the wafer can be exposed in this manner if damage and/or unwanted wafer surface patterns are to be avoided. A more convenient and complete monitoring of the wafer is being sought.